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? semiconductor components industries, llc, 2014 october, 2014 ? rev. 4 1 publication order number: ncv4275a/d ncv4275a 5.0 v, 3.3 v 450 ma low-dropout voltage regulator with reset the ncv4275a is an integrated low dropout regulator designed for use in harsh automotive environments. it includes wide operating temperature and input voltage ranges. the output is regulated at 5.0 v or 3.3 v and is rated to 450 ma of output current. it also provides a number of features, including overcurrent protection, overtemperature protection and a programmable microprocessor reset. the ncv4275a is available in the dpak and d 2 pak surface mount packages. the output is stable over a wide output capacitance and esr range. the ncv4275a is pin for pin compatible with ncv4275. features ? 5.0 v and 3.3 v, 2% output voltage options ? 450 ma output current ? very low current consumption ? active reset output ? reset low down to v q = 1.0 v ? 500 mv (max) dropout voltage ? fault protection ? +45 v peak transient voltage ? ?42 v reverse voltage ? short circuit protection ? thermal overload protection ? aec?q100 grade 1 qualified and ppap capable ? pin compatible with ncv4275 ? these are pb?free devices applications ? auto body electronics + ? i d q gnd ro current limit and saturation sense bandgap reference thermal shutdown reset generator figure 1. block diagram error amplifier d 2 pak, 5?pin ds suffix case 936a 1 5 dpak, 5?pin dt suffix case 175aa pin 1. i 2. ro tab, 3. gnd* 4. d 5. q * tab is connected to pin 3 on all packages ordering information 1 5 marking diagrams 1 1 x = 5 (5.0 v output) or 3 (3.3 v output) a = assembly location wl, l = wafer lot y = year ww = work week g = pb?free package 4275axg alyww nc v4275ax awlywwg see detailed ordering and shipping information in the dimensions section on page 17 of this data sheet. www. onsemi.com
ncv4275a www. onsemi.com 2 pin function description pin # symbol description ???? ???? 1 ??? ??? ???????????????????????????? ???????????????????????????? ???? ???? ??? ??? ???????????????????????????? ???????????????????????????? ???? ???? ??? ??? ???????????????????????????? ???????????????????????????? ???? ???? ??? ??? ???????????????????????????? ???????????????????????????? ???? ???? ??? ??? ???????????????????????????? ???????????????????????????? 2.0%, 450 ma output. bypass with 22 f capacitor, esr < 4.5 (5.0 v version), 3.5 (3.3 v version) to ground. maximum ratings rating symbol min max unit input v oltage v i ?42 45 v input peak t ransient v oltage v i ? 45 v output v oltage v q ?1.0 16 v reset output voltage v ro ?0.3 25 v reset output current i ro ?5.0 5.0 ma reset delay voltage v d ?0.3 7.0 v reset delay current i d ?2.0 2.0 ma esd susceptibility (note 1) ? human body model ? machine model ? charge device model esd hbm esd mm esd cdm 4.0 200 1000 ? ? ? kv v v junction t emperature t j ?40 150 c storage t emperature t stg ?55 150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. 1. this device incorporates esd protection and is tested by the following methods: esd human body model tested per aec?q100?002, esd machine model tested per aec?q100?003, esd charged device model tested per aec?q100?011, latch?up tested per aec?q100?004.
ncv4275a www. onsemi.com 3 operating range input v oltage operating range, 5.0 v output v i 5.5 42 v input voltage operating range, 3.3 v output v i 4.4 42 v junction t emperature t j ?40 150 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond th e recommended operating ranges limits may affect device reliability. lead temperature soldering reflow and msl (note 2) lead free, 60 sec?150 sec above 217 c t sld ? 265 peak c moisture sensitivity level msl 1 thermal characteristics characteristic test conditions (typical v alue) unit dpak 5?pin p ackage min pad board (note 3) 1 pad board (note 4) junction?to?tab (r jt ) 4.2 4.7 c/w junction?to?ambient (r ja ) 100.9 46.8 c/w d 2 pak 5?pin p ackage 0.4 sq. in. spreader board (note 5) 1.2 sq. in. spreader board (note 6) junction?to?tab (r jt ) 3.8 4.0 c/w junction?to?ambient (r ja ) 74.8 41.6 c/w 2. pr r ipc / jedec j?std?020c 3. 1 oz. copper, 0.26 inch 2 (168 mm 2 ) copper area, 0.062 thick fr4. 4. 1 oz. copper, 1.14 inch 2 (736 mm 2 ) copper area, 0.062 thick fr4. 5. 1 oz. copper, 0.373 inch 2 (241 mm 2 ) copper area, 0.062 thick fr4. 6. 1 oz. copper, 1.222 inch 2 (788 mm 2 ) copper area, 0.062 thick fr4.
ncv4275a www. onsemi.com 4 electrical characteristics (v i = 13.5 v; ?40 c < t j < 150 c; unless otherwise noted.) characteristic symbo l test conditions 5.0v output voltage 3.3v output voltage unit min typ max min typ max output output v oltage v q 100 a i q 400 ma 6.0v v i 28v (5.0v version) 4.4v v i 28v (3.3v version) 4.9 5.0 5.1 3.23 3.3 3.37 v output v oltage v q 100 a i q 200 ma 6.0v v i 40v (5.0v version) 4.4v v i 40v (3.3v version) 4.9 5.0 5.1 3.23 3.3 3.37 v output current limitation i q v q = 0.9 x v q,typ 450 700 ? 450 700 ? ma quiescent current i q = i i ? i q i q i q = 1.0 ma ? 140 200 ? 135 200 a i q = 1.0 ma, t j = 25 c ? 140 150 ? 135 150 a i q = 250 ma ? 10 15 ? 10 15 ma i q = 400 ma ? 23 35 ? 23 35 ma dropout v oltage v dr i q = 300 ma v dr = v i ? v q (note 7) ? 250 500 ? 1100 1170 mv load regulation v q i q = 5.0 ma to 400 ma ?30 15 30 ?30 15 30 mv line regulation v q v i = 8.0 v to 32 v, i q = 5.0 ma ?15 5.0 15 ?15 5.0 15 mv power supply ripple rejection psrr f r = 100 hz, v r = 0.5 v pp ? 60 ? ? 60 ? db temperature output v oltage drift dv q /dt ?? ? 0.5 ? ? 0.5 ? mv/k reset timing d and output ro reset switching threshold v q,rt ?? 4.53 4.65 4.8 3.0 3.1 3.2 v reset output low voltage v rol r ext 5.0 k , v q 1.0v ? 0.2 0.4 ? 0.2 0.4 v reset output leakage current i roh v roh = 5.0v ? 0 10 ? 0 10 a reset charging current i d,c v d = 1.0v 3.0 5.5 9.0 2.0 4.0 9.0 a upper timing threshold v du ?? 1.5 1.8 2.2 0.7 1.3 1.6 v lower timing threshold v dl ?? 0.2 0.4 0.7 0.2 0.4 0.7 v reset delay time t rd c d = 47nf 10 16 22 10 16 22 ms reset reaction time t rr c d = 47nf ? 1.5 4.0 ? 1.5 4.0 s thermal shutdown shutdown temperature (note 8) t sd ?? 150 ? 210 150 ? 210 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. measured when output voltage v q falls 100 mv below the regulated voltage at v i = 13.5 v. v dr = v i ? v q .for output voltage set < 4.4 v, v dr will be constrained by the minimum input voltage. 8. guaranteed by design, not tested in production.
ncv4275a www. onsemi.com 5 typical performance characteristics figure 2. output stability with output capacitor esr figure 3. output stability with output capacitor esr figure 4. output stability with output capacitor esr figure 5. output stability with output capacitor esr figure 6. output voltage v q vs. temperature t j figure 7. output voltage v q vs. temperature t j 0.01 0.1 1 10 i q , output current (ma) esr ( ) c q = 22 f stable esr region 0 100 200 300 400 v q(nom) = 5.0 v c q = 22 f stable esr region 0 100 200 300 400 v q(nom) = 3.3 v 0.01 0.1 1 10 i q , output current (ma) esr ( ) 0.1 1 10 100 0.01 i q , output current (ma) esr ( ) c q = 1 f stable esr region 0 100 200 300 400 v q(nom) = 5.0 v 0.1 1 10 100 i q , output current (ma) esr ( ) c q = 1 f stable esr region 0 100 200 300 400 v q(nom) = 3.3 v v q , output volage (v) t j , junction temperature ( c) v i = 13.5 v, r l = 25 4.9 5.0 5.1 5.2 4.8 ?40 0 40 80 120 v q(nom) = 5.0 v 160 v q , output volage (v) t j , junction temperature ( c) v i = 13.5 v, r l = 16.5 3.2 3.3 3.4 3.5 3.1 ?40 0 40 80 120 v q(nom) = 3.3 v 160 5.0 v version 3.3 v version
ncv4275a www. onsemi.com 6 typical performance characteristics figure 8. output voltage v q vs. input voltage v i figure 9. output voltage v q vs. input voltage v i figure 10. output current i q vs. temperature t j figure 11. output current i q vs. temperature t j figure 12. output current i q vs. input voltage v i figure 13. output current i q vs. input voltage v i v q , output voltage (v) v i , input voltage (v) r l = 25 t j = 25 c 1.0 3.0 5.0 6.0 0.0 02468 v q(nom) = 5.0 v 10 2.0 4.0 v q , output voltage (v) v i , input voltage (v) r l = 16.5 t j = 25 c 1.0 3.0 5.0 6.0 0.0 0 2468 v q(nom) = 3.3 v 10 2.0 4.0 i q , output current limitation (a) t j , junction temperature ( c) v i = 13.5 v 0.2 0.4 0.6 0.8 0.0 ?40 0 40 80 120 v q(nom) = 5.0 v 160 1.0 1.2 i q , output current limitation (a) t j , junction temperature ( c) v i = 13.5 v 0.2 0.4 0.6 0.8 0.0 ?40 0 40 80 120 v q(nom) = 3.3 v 160 1.0 1.2 i q , output current limitation (a) v i , input voltage (v) 0.2 0.4 0.6 0.8 0.0 010203040 v q(nom) = 5.0 v 50 1.0 1.2 t j = 125 c t j = 25 c i q , output current limitation (a) v i , input voltage (v) 0.2 0.4 0.6 0.8 0.0 010203040 v q(nom) = 3.3 v 50 1.0 1.2 t j = 125 c t j = 25 c 5.0 v version 3.3 v version
ncv4275a www. onsemi.com 7 typical performance characteristics figure 14. current consumption i q vs. output current i q figure 15. current consumption i q vs. output current i q i q , current consumption (ma) i q , output current (ma) v i = 13.5 v, t j = 25 c figure 16. current consumption i q vs. output current i q figure 17. current consumption i q vs. output current i q figure 18. charge current i d,c vs. temperature t j figure 19. charge current i d,c vs. temperature t j 0.5 1.0 1.5 2.0 0.0 0 20 40 80 100 v q(nom) = 5.0 v 120 2.5 3.5 3.0 60 i q , current consumption (ma) i q , output current (ma) v i = 13.5 v, t j = 25 c 10 20 30 40 0 0 100 200 400 500 v q(nom) = 5.0 v 600 50 80 60 300 70 i dc , charge current ( a) t j , junction temperature ( c) v i = 13.5 v, v d = 1.0 v 1 2 3 4 0 ?40 0 40 80 120 v q(nom) = 5.0 v 160 5 6 i q , current consumption (ma) i q , output current (ma) v i = 13.5 v, t j = 25 c 0.5 1.0 1.5 2.0 0.0 0 20 40 80 100 v q(nom) = 3.3 v 12 0 2.5 3.5 3.0 60 i q , current consumption (ma) i q , output current (ma) v i = 13.5 v, t j = 25 c 10 20 30 40 0 0 100 200 400 500 v q(nom) = 3.3 v 60 0 50 80 60 300 70 7 8 i dc , charge current ( a) t j , junction temperature ( c) v i = 13.5 v, v d = 1.0 v 1 2 3 4 0 ?40 0 40 80 120 v q(nom) = 3.3 v 16 0 5 6 5.0 v version 3.3 v version
ncv4275a www. onsemi.com 8 typical performance characteristics figure 20. delay switching threshold v du , v dl vs. temperature t j figure 21. delay switching threshold v du , v dl vs . temperature t j figure 22. drop voltage v dr vs. output current i q v du/ v dl , upper/lower timing threshold (v) t j , junction temperature ( c) v i = 13.5 v v du v dl 0.2 0.4 0.6 0.8 0.0 ?40 0 40 120 v q(nom) = 5.0 v 160 1.0 1.2 1.4 1.6 1.8 2.0 80 v du/ v dl , upper/lower timing threshold (v) t j , junction temperature ( c) v i = 13.5 v v du v dl 0.2 0.4 0.6 0.8 0.0 ?40 0 40 120 v q(nom) = 3.3 v 16 0 1.0 1.2 1.4 80 v dr , dropout voltage (mv) i q , output current (ma) t j = 125 c 100 200 300 400 0 0 100 200 400 500 v q(nom) = 5.0 v 700 500 700 600 300 600 t j = 25 c 5.0 v version 3.3 v version
ncv4275a www. onsemi.com 9 application information v i c i1 1000 f c i2 100 nf c d 47 nf i i i d i d 1 4 5 2 3 gnd c q 22 f i ro i q q ro r ext 5.0 k v q v ro figure 23. test circuit ncv4275a i q circuit description the ncv4275a is an integrated low dropout regulator that provides 5.0 v or 3.3 v, 450 ma protected output and a signal for power on reset. the regulation is provided by a pnp pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible drop out voltage and best possible temperature stability. the output current capability is 450 ma, and the base drive quiescent current is controlled to prevent over saturation when the input voltage is low or when the output is overloaded. the regulator is protected by both current limit and thermal shutdown. thermal shutdown occurs above 150 c to protect the ic during overloads and extreme ambient temperatures. the delay time for the reset output is adjustable by selection of the timing capacitor. see figure 23, test circuit, for circuit element nomenclature illustration. regulator the error amplifier compares the reference voltage to a sample of the output voltage (v q ) and drives the base of a pnp series pass transistor by a buffer. the reference is a bandgap design to give it a temperature?stable output. saturation control of the pnp is a function of the load current and input voltage. over saturation of the output power device is prevented, and quiescent current in the ground pin is minimized. regulator stability considerations the input capacitors (c i1 and c i2 ) are necessary to stabilize the input impedance to avoid voltage line influences. using a resistor of approximately 1.0 in series with c i2 can stop potential oscillations caused by stray inductance and capacitance. the output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum, aluminum or ceramic capacitors can be used. the range of stability versus capacitance, load current and capacitive esr is illustrated in figures 2 to 5. minimum esr for c q = 22 f is native esr of ceramic capacitors. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (?25 c to ?40 c), both the capacitance and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for the output capacitor c q shown in figure 23, test circuit, should work for most applications; however, it is not necessarily the optimized solution. stability is guaranteed for c q 22 f and an esr 4.5 (5.0 v version), 3.5 (3.3 v version). esr characteristics were measured with ceramic capacitors and additional resistors to emulate esr. murata ceramic capacitors were used, grm32er71a226me20 (22 f, 10 v, x7r, 1210), grm31mr71e105ka01 (1 f, 25 v, x7r, 1206). reset output the reset output is used as the power on indicator to the microcontroller. this signal indicates when the output voltage is suitable for reliable operation of the controller. it pulls low when the output is not considered to be ready. ro is pulled up to v q by an external resistor, typically 5.0 k in value. the input and output conditions that control the reset output and the relative timing are illustrated in figure 24, reset timing. output voltage regulation must be maintained for the delay time before the reset output signals a valid condition. the delay for the reset output is defined as the amount of time it takes the timing capacitor on the delay pin to charge from a residual voltage of 0.0 v to the upper timing threshold voltage v du . the charging current for this is i d,c and d pin voltage in steady state is typically 3.2 v for 5.0 v regulator and typically 2.4 v for 3.3 v regulator. by using typical ic parameters with a 47 nf capacitor on the d pin, the following time delay for 5.0 v regulator is derived: t rd = c d v du / i d,c t rd = 47 nf (1.8 v) / 5.5 a = 15.4 ms other time delays can be obtained by changing the capacitor value.
ncv4275a www. onsemi.com 10 figure 24. reset timing v i v q v d v ro reset delay time reset reaction time power?on?reset thermal shutdown voltage dip at input undervoltage secondary spike overload at output < reset reaction time t t t t v q,rt upper timing threshold v du lower timing threshold v dl dv d dt reset charge current c d
ncv4275a www. onsemi.com 11 calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 25) is: p d(max) [v i(max) v q(min) ]i q(max) ( 1) v i(max) i q where v i(max) is the maximum input voltage, v q(min) is the minimum output voltage, i q(max) is the maximum output current for the application, i q is the quiescent current the regulator consumes at i q(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. smart regulator ? iq control features i q i i figure 25. single output regulator with key performance parameters labeled v i v q } heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where r jc is the junction?to?case thermal resistance, r cs is the case?to?heatsink thermal resistance, r sa is the heatsink?to?ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heatsink manufacturers. thermal, mounting, and heatsinking considerations are discussed in the on semiconductor application note an1040/d. thermal model a discussion of thermal modeling is in the on semiconduc tor web site: http://www.onsem i.com/pub/collateral/br1487?d.pdf. table 1. dpak 5?lead thermal rc network models drain copper area (1 oz thick) 168 mm 2 736 mm 2 168 mm 2 736 mm 2 (spice deck format) cauer network foster network 168 mm 2 736 mm 2 units ta u ta u units c_c1 junction gnd 1.00e?06 1.00e?06 w?s/c 1.36e?08 1.361e?08 sec c_c2 node1 gnd 1.00e?05 1.00e?05 w?s/c 7.41e?07 7.41 1e?07 sec c_c3 node2 gnd 6.00e?05 6.00e?05 w?s/c 1.04e?05 1.029e?05 sec c_c4 node3 gnd 1.00e?04 1.00e?04 w?s/c 3.91e?05 3.737e?05 sec c_c5 node4 gnd 4.36e?04 3.64e?04 w?s/c 1.80e?03 1.376e?03 sec c_c6 node5 gnd 6.77e?02 1.92e?02 w?s/c 3.77e?01 2.851e?02 sec c_c7 node6 gnd 1.51e?01 1.27e?01 w?s/c 3.79e+00 9.475e?01 sec c_c8 node7 gnd 4.80e?01 1.018 w?s/c 2.65e+01 1.173e+01 sec c_c9 node8 gnd 3.740 2.955 w?s/c 8.71e+01 8.59e+01 sec
ncv4275a www. onsemi.com 12 (spice deck format) foster network cauer network c_c10 node9 gnd 10.322 0.438 w?s/c sec 168 mm 2 736 mm 2 r?s r?s r_r1 junction node1 0.015 0.015 c/w 0.0123 0.0123 c/w r_r2 node1 node2 0.08 0.08 c/w 0.0585 0.0585 c/w r_r3 node2 node3 0.4 0.4 c/w 0.0304 0.0287 c/w r_r4 node3 node4 0.2 0.2 c/w 0.3997 0.3772 c/w r_r5 node4 node5 2.97519 2.6171 c/w 3.115 2.68 c/w r_r6 node5 node6 8.2971 1.6778 c/w 3.571 1.38 c/w r_r7 node6 node7 25.9805 7.4246 c/w 12.851 5.92 c/w r_r8 node7 node8 46.5192 14.9320 c/w 35.471 7.39 c/w r_r9 node8 node9 17.7808 19.2560 c/w 46.741 28.94 c/w r_r10 node9 gnd 0.1 0.1758 c/w c/w note: bold face items represent the package without the external thermal system. junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n time constants are not simple rc products. amplitudes of mathematical solution are not the resistance values. ambient (thermal ground) figure 26. grounded capacitor thermal network (?cauer? ladder) junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n each rung is exactly characterized by its rc?product time constant; amplitudes are the resistances. ambient (thermal ground) figure 27. non?grounded capacitor thermal ladder (?foster? ladder)
ncv4275a www. onsemi.com 13 table 2. d 2 pak 5?lead thermal rc network models drain copper area (1 oz thick) 241 mm 2 788 mm 2 241 mm 2 788 mm 2 (spice deck format) cauer network foster network 241 mm 2 653 mm 2 units ta u ta u units c_c1 junction gnd 1.00e?06 1.00e?06 w?s/c 1.361e?08 1.361e?08 sec c_c2 node1 gnd 1.00e?05 1.00e?05 w?s/c 7.41 1e?07 7.41 1e?07 sec c_c3 node2 gnd 6.00e?05 6.00e?05 w?s/c 1.005e?05 1.007e?05 sec c_c4 node3 gnd 1.00e?04 1.00e?04 w?s/c 3.460e?05 3.480e?05 sec c_c5 node4 gnd 2.82e?04 2.87e?04 w?s/c 7.868e?04 8.107e?04 sec c_c6 node5 gnd 5.58e?03 5.95e?03 w?s/c 7.431e?03 7.830e?03 sec c_c7 node6 gnd 4.25e?01 4.61e?01 w?s/c 2.786e+00 2.012e+00 sec c_c8 node7 gnd 9.22e?01 2.05 w?s/c 2.014e+01 2.601e+01 sec c_c9 node8 gnd 1.73 4.88 w?s/c 1.134e+02 1.218e+02 sec c_c10 node9 gnd 7.12 1.31 w?s/c sec 241 mm 2 653 mm 2 r?s r?s r_r1 junction node1 0.015 0.0150 c/w 0.0123 0.0123 c/w r_r2 node1 node2 0.08 0.0800 c/w 0.0585 0.0585 c/w r_r3 node2 node3 0.4 0.4000 c/w 0.0257 0.0260 c/w r_r4 node3 node4 0.2 0.2000 c/w 0.3413 0.3438 c/w r_r5 node4 node5 1.85638 1.8839 c/w 1.77 1.81 c/w r_r6 node5 node6 1.23672 1.2272 c/w 1.54 1.52 c/w r_r7 node6 node7 9.81541 5.3383 c/w 4.13 3.46 c/w r_r8 node7 node8 33.1868 18.9591 c/w 6.27 5.03 c/w r_r9 node8 node9 27.0263 13.3369 c/w 60.80 29.30 c/w r_r10 node9 gnd 1.13944 0.1191 c/w c/w note: bold face items represent the package without the external thermal system. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1?e ?t tau i
ncv4275a www. onsemi.com 14 110 150 figure 28. ja vs. copper spreader area, dpak 5?lead figure 29. ja vs. copper spreader area, d 2 pak 5?lead 100 90 80 70 60 50 40 30 200 250 300 350 400 450 500 550 600 650 700 750 copper area (mm 2 ) ja (c /w) 1 oz 2 oz 110 150 100 90 80 70 60 50 40 30 200 250 300 350 400 450 500 550 600 650 700 75 0 copper area (mm 2 ) ja (c /w) 1 oz 2 oz 100 10 1.0 0.1 0.01 time (sec) r(t) c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 cu area 167 mm 2 cu area 736 mm 2 figure 30. single?pulse heating curves, dpak 5?lead 100 10 1.0 0.1 0.01 time (sec) r(t) c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 cu area 167 mm 2 cu area 736 mm 2 sqrt(t) figure 31. single?pulse heating curves, d 2 pak 5?lead
ncv4275a www. onsemi.com 15 100 10 1.0 0.1 0.01 pulse width (sec) r ja 788 mm 2 c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 non?normalized response 50% duty cycle 20% 10% 5% 2% 1% 100 10 1.0 0.1 0.01 pulse width (sec) r ja 736 mm 2 c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 non?normalized response 50% duty cycle figure 32. duty cycle for 1? spreader boards, dpak 5?lead 20% 10% 5% 2% 1% figure 33. duty cycle for 1? spreader boards, d 2 pak 5?lead
ncv4275a www. onsemi.com 16 emc?characteristics: conducted susceptibility all emc?characteristics are based on limited samples and no part of production test according to 47a/658/cd iec62132?4 (direct power injection). test conditions supply voltage v in = 12 v temperature t a = 23 c 5 c load r l = 100 direct power injection 33 dbm (note 1) forward power cw for global pin (note 2) 17 dbm (note 1) forward power cw for local pin (note 3) acceptance criteria amplitude dev. max 4% of output voltage reset outputs remain in correct state 1 v 1. dbm means db mili?watts, p(dbm) = 10 log (p(mw)). 2. a global pin carries a signal or power which enters or leaves the application board. 3. a local pin carries a signal or power which does not leave the application board. it remains on the application board as a signal between two components. figure 34. test circuit c6 47 nf x8 d_hf x7 d_dc x6 vout_hf c4 47 nf x5 vout_dc c5 22 f ferrite l3 ferrite l1 ferrite l2 ferrite l4 x4 ro_hf x3 ro_dc x2 vin_hf x1 vin_dc r1 4.99k vout 1 2 5 4 3 i ro q d gnd ncv4275a u1 vout c2 10 f c1 100 nf
ncv4275a www. onsemi.com 17 1 figure 35. typical v in pin susceptibility figure 36. typical v out pin susceptibility 40 30 20 10 0 10 100 1000 frequency (mhz) (dbm) v in pass 33 dbm 25 1 figure 37. typical r o pin susceptibility figure 38. typical delay pin susceptibility 20 15 10 5 0 10 100 1000 frequency (mhz) (dbm) r o pass 17 dbm 25 1 20 15 10 5 0 10 100 100 0 frequency (mhz) (dbm) delay pass 17 dbm 1 40 30 20 10 0 10 100 10 00 frequency (mhz) (dbm) v out pass 33 dbm ordering information device output v oltage package shipping ? ncv4275ads50g 5.0 v d 2 pak (pb?free) 50 units/rail ncv4275ads50r4g 800 tape & reel ncv4275adt50rkg dpak (pb?free) 2500 tape & reel ncv4275ads33g 3.3 v d 2 pak (pb?free) 50 units/rail ncv4275ads33r4g 800 tape & reel NCV4275ADT33RKG dpak (pb?free) 2500 tape & reel ?for information on tape and reel specifications,including part orientation and tape sizes, please refer to our tape and reel p ackaging specifications brochure, brd801 1/d.
ncv4275a www. onsemi.com 18 package dimensions d a k b r v s f l g 5 pl m 0.13 (0.005) t e c u j h ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.020 0.028 0.51 0.71 e 0.018 0.023 0.46 0.58 f 0.024 0.032 0.61 0.81 g 0.180 bsc 4.56 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.045 bsc 1.14 bsc r 0.170 0.190 4.32 4.83 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 0.170 3.93 4.32 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. r1 0.185 0.210 4.70 5.33 r1 1234 5 dpak 5, center lead crop dt suffix case 175aa?01 issue a 6.4 0.252 0.8 0.031 10.6 0.417 5.8 0.228 scale 4:1 mm inches 0.34 0.013 5.36 0.217 2.2 0.086 soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d.
ncv4275a www. onsemi.com 19 package dimensions d 2 pak, 5 lead ds suffix case 936a?02 issue c 5 ref a 123 k b s h d g c e m l p n r v u terminal 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions a and k. 4. dimensions u and v establish a minimum mounting surface for terminal 6. 5. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) maximum. dim a min max min max millimeters 0.386 0.403 9.804 10.236 inches b 0.356 0.368 9.042 9.347 c 0.170 0.180 4.318 4.572 d 0.026 0.036 0.660 0.914 e 0.045 0.055 1.143 1.397 g 0.067 bsc 1.702 bsc h 0.539 0.579 13.691 14.707 k 0.050 ref 1.270 ref l 0.000 0.010 0.000 0.254 m 0.088 0.102 2.235 2.591 n 0.018 0.026 0.457 0.660 p 0.058 0.078 1.473 1.981 r 5 ref s 0.116 ref 2.946 ref u 0.200 min 5.080 min v 0.250 min 6.350 min 45 m 0.010 (0.254) t ?t? optional chamfer 8.38 0.33 1.016 0.04 16.02 0.63 10.66 0.42 3.05 0.12 1.702 0.067 scale 3:1 mm inches soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. ncv4275a/d p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent? marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or othe r applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death ma y occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidi aries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of per sonal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. sci llc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.

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